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?2006 silicon storage technology, inc. s71310-00-000 6/06 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. combomemory is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. data sheet features: ? flash organization: 2m x16 ? 32 mbit: 24mbit + 8mbit ? concurrent operation ? read from or write to sram while erase/program flash ? sram organization: ? 4 mbit: 256k x16 ? single 2.7-3.3v read and write operations ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption: (typical values @ 5 mhz) ? active current: flash 10 ma (typical) sram 6 ma (typical) ? standby current: 10 a (typical) ? hardware sector protection (wp#) ? protects 4 outer most sectors (8 kword) in the smaller bank by holding wp# low and unprotects by holding wp# high ? hardware reset pin (rst#) ? resets the internal state machine to reading data array ? sector-erase capability ? uniform 2 kword sectors ? block-erase capability ? uniform 32 kword blocks ? read access time ? flash: 70 ns ?sram: 70 ns ? erase-suspend / erase-resume capabilities ? latched address and data ? fast erase and word-program (typical): ? sector-erase time: 18 ms ? block-erase time: 18 ms ? chip-erase time: 35 ms ? program time: 7 s ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bit ? data# polling ? cmos i/o compatibility ? jedec standard command set ? packages available ? 48-ball lfbga (6mm x 8mm) ? all non-pb (lead-free) devices are rohs compliant product description the sst34hf324g combomemory devices integrate a 2m x16 cmos flash memory bank with 256k x16 cmos sram memory bank in a multi-chip package (mcp). these devices are fabricated using sst?s proprietary, high- performance cmos superflash technology incorporating the split-gate cell design and thick-oxide tunneling injector to attain better reliabilit y and manufacturability compared with alternate approaches. the sst34hf324g devices are ideal for applications such as cellular phones, gps devices, pdas, and other portable electronic devices in a low power and small form factor system. the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/pro- gram cycles. the sst34hf324g devices offer a guaran- teed endurance of 10,000 cycles. data retention is rated at greater than 100 years. with high-performance program operations, the flash memory banks provide a typical pro- gram time of 7 sec. the entire flash memory bank can be erased and programmed word-by-word in 4 seconds (typi- cally) for the sst34hf324g, when using interface features such as toggle bit or data# polling to indicate the comple- tion of program operation. to protect against inadvertent flash write, the sst34hf324g devices contain on-chip hardware and software data protection schemes. the flash and sram operate as two independent memory banks with respective bank enable signals. the memory bank selection is done by two bank enable signals. the sram bank enable signal, bes# , selects the sram bank. the flash memory bank enable signal, bef#, has to be used with software data protection (sdp) command sequence when controlling the erase and program opera- tions in the flash memory bank. the memory banks are superimposed in the same memory address space where they share common address lines, data lines, we# and oe# which minimize power consumption and area. see table 3 for memory organization. 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g sst34hf324g32mb dual-bank flash + 4 mb sram mcp combomemory
2 data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g ?2006 silicon storage technology, inc. s71310-00-000 6/06 designed, manufactured, and tested for applications requir- ing low power and small form factor, the sst34hf324g are offered in both commercial and extended temperatures and a small footprint package to meet board space con- straint requirements. see figure 2 for pin assignments. device operation the sst34hf324g use bes# and bef# to control opera- tion of either the flash or the sram memory bank. when bef# is low, the flash bank is activated for read, program or erase operation. when bes# is low the sram is acti- vated for read and write operation. bef# and bes# can- not be at low level at the same time. if all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. all address, data, and control lines are shared by flash and sram memory banks which minimi zes power consumption and loading. the device goes into standby when bef# and bes# bank enables are raised to v ihc (logic high) or when bef# is high. concurrent read/write operation the sst34hf324g provide the unique benefit of being able to read from or write to sram, while simultaneously erasing or programming the flash. this allows data alter- ation code to be executed from sram, while altering the data in flash. the following table lists all valid states. the device will ignore all sdp commands when an erase or program operation is in progress. note that product identification commands use sdp; therefore, these com- mands will also be ignored while an erase or program operation is in progress. flash read operation the read operation of the sst34hf324g is controlled by bef# and oe#, both have to be low for the system to obtain data from the outputs. bef# is used for device selection. when bef# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either bef# or oe# is high. refer to the read cycle timing diagram for further details (figure 6). flash program operation these devices are programmed on a word-by-word basis. before programming, one must ensure that the sector which is being programmed is fully erased. the program operation is accomplished in three steps: 1. software data protection is initiated using the three-byte load sequence. 2. address and data are loaded. during the program operation, the addresses are latched on the fa lling edge of either bef# or we#, whichever occurs last. the data is latched on the rising edge of either bef# or we#, whichever occurs first. 3. the internal program oper ation is initiated after the rising edge of the fourth we# or bef#, which- ever occurs first. the program operation, once ini- tiated, will be completed typically within 7 s. see figures 7 and 8 for we# and bef# controlled pro- gram operation timing diagrams and figure 20 for flow- charts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal pro- gram operation, the host is free to perform additional tasks. any commands issued during an internal program opera- tion are ignored. flash sector- /block -erase operation these devices offer both sector-erase and block-erase operations. these operations allow the system to erase the devices on a sector-by-sector (or block-by-block) basis. the sector architecture is based on a uniform sector size of 2 kword. the block-erase mode is based on a uniform block size of 32 kword. the sector-erase operation is initi- ated by executing a six-byte command sequence with a sector-erase command (50h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by executing a six-byte command sequence with block-erase command (30h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. any commands issued during the block- or sector- erase operation are ignored except erase-suspend and erase-resume. see figures 12 and 13 for timing wave- forms. concurrent read/write state table flash sram program/erase read program/erase write
data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g 3 ?2006 silicon storage technology, inc. s71310-00-000 6/06 flash chip-erase operation the sst34hf324g provide a chip-erase operation, which allows the user to erase all sectors/blocks to the ?1? state. this is useful when the device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or bef#, whichever occurs first. during the erase operation, the only valid read is toggle bits or data# polling. see table 6 for the command sequence, figure 11 for timing diagram, and figure 23 for the flowchart. any commands issued during the chip-erase operation are ignored. flash erase-suspend/-r esume operations the erase-suspend operation temporarily suspends a sector- or block-erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an erase operation. the operation is executed by issuing a one-byte command sequence with erase-suspend command (b0h). the device automatically enters read mode within 20 s after the erase-suspend command had been issued. valid data can be read from any sector or block that is not suspended from an erase operation. reading at address location within erase-suspended sect ors/blocks will output dq 2 tog- gling and dq 6 at ?1?. while in erase-suspend mode, a pro- gram operation is allowed except for the sector or block selected for erase-suspend. to resume sector-erase or block-erase operation which has been suspended, the system must issue an erase-resume command. the operation is executed by issuing a one-byte command sequence with erase resume command (30h) at any address in the one-byte sequence. flash write operati on status detection the sst34hf324g provides two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the software detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling (dq 7 ) or toggle bit (dq 6 ) read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to pre- vent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. flash data# polling (dq 7 ) when the device is in an internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. during internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or bef#) pulse for program operation. for sector-, block-, or chip-erase, the data# polling is valid after the rising edge of sixth we# (or bef#) pulse. see figure 9 for data# poll- ing (dq 7 ) timing diagram and figure 21 for a flowchart. toggle bits (dq 6 and dq 2 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating ?1?s and ?0?s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the device is then ready for the next opera- tion. the toggle bit is valid after the rising edge of the fourth we# (or bef#) pulse for program operations. for sector-, block-, or chip-erase, the toggle bit (dq 6 ) is valid after the rising edge of sixth we# (or bef#) pulse. dq 6 will be set to ?1? if a read operation is attempted on an erase-sus- pended sector/block. if program operation is initiated in a sector/block not selected in erase-suspend mode, dq 6 will toggle. an additional toggle bit is available on dq 2 , which can be used in conjunction with dq 6 to check whether a particular sector is being actively erased or erase-suspended. table 1 shows detailed status bit information. the toggle bit (dq 2 ) is valid after the rising edge of the last we# (or bef#) pulse of a write operation. see figure 10 for toggle bit tim- ing diagram and figure 21 for a flowchart.
4 data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g ?2006 silicon storage technology, inc. s71310-00-000 6/06 note: dq 7, dq 6, and dq 2 require a valid address when reading status information. data protection the sst34hf324g provide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or bef# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, bef# high, or we# high will inhibit t he write operation. th is prevents inadvert- ent writes during power-up or power-down. hardware block protection the sst34hf324g provide a hardware block protection which protects the outermost 8 kword in bank 1. the block is protected when wp# is held low. see figure 3 for block- protection location. a user can disable block protection by driving wp# high thus allowing erase or program of data into the protected sectors. wp# must be held high prior to issuing the write command and remain stable until after the entire write operation has completed. hardware reset (rst#) the rst# pin provides a hardware method of resetting the device to read array data. when the rst# pin is held low for at least t rp, any in-progress operat ion will terminate and return to read mode (see figure 17). when no internal program/erase operation is in progress, a minimum period of t rhr is required after rst# is driven high before a valid read can take place (see figure 16). the erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. see figures 16 and 17 for timing diagrams. software data protection (sdp) the sst34hf324g provide the jedec standard soft- ware data protection scheme for all data alteration opera- tions, i.e., program and erase. any program operation requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte sequence. the sst34hf324g are shipped with the software data protection permanently enabled. see table 6 for the specific software command codes. during sdp command sequence, invali d commands will abort the device to read mode within t rc. the contents of dq 15 - dq 8 are ?don?t care? during any sdp command sequence. table 1: write operation status status dq 7 dq 6 dq 2 normal operation standard program dq7# toggle no toggle standard erase 0 toggle toggle erase- suspend mode read from erase suspended sector/ block 1 1 toggle read from non-erase suspended sector/ block data data data program dq7# toggle no toggle t1.0 1310
data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g 5 ?2006 silicon storage technology, inc. s71310-00-000 6/06 product identification the product identification mode identifies the device as sst34hf324g and the manufacturer as sst. this mode may be accessed by software operations only. the hard- ware device id read operation, which is typically used by programmers cannot be used on this device because of the shared lines between flash and sram in the multi-chip package. therefore, application of high voltage to pin a 9 may damage this device. users may use the software product identification operation to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, see tables 5 and 6 for soft- ware operation, figure 14 for the software id entry and read timing diagram and figure 22 for the id entry com- mand sequence flowchart. note: bk = bank address (a 20 -a 18 ) product identification mode exit in order to return to the standard read mode, the software product identification mode must be exited. exit is accom- plished by issuing the software id exit command sequence, which returns the device to the read mode. this command may also be used to reset the device to the read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. please note that the software id exit command is ignored during an internal program or erase operation. see table 6 for software command codes, fig- ure 15 for timing waveform and figure 22 for a flowchart. sram operation with bes# low and bef# high, the sst34hf324g oper- ates as either 256k x16 cmos sram, with fully static operation requiring no external clocks or timing strobes. when bes# and bef# are high, all memory banks are deselected and the device enters standby. read and write cycle times are equal. the control signals ubs# and lbs# provide access to the upper data byte and lower data byte. see table 5 for sram read and write data byte control modes of operation. sram read the sram read operation of the sst34hf324g is con- trolled by oe# and bes#, both have to be low with we# high for the system to obtain data from the outputs. bes# is used for sram bank selection. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. refer to the read cycle timing diagram, figure 3, for further details. sram write the sram write operation of the sst34hf324g is con- trolled by we# and bes#, both have to be low for the sys- tem to write to the sram. during the word-write operation, the addresses and data are referenced to the rising edge of either bes# or we# whichever occurs first. the write time is measured from the last falling edge of bes# or we# to the first rising edge of bes# or we#. refer to the write cycle timing diagrams, figures 4 and 5, for further details. table 2: product identification address data manufacturer?s id bk0000h 00bfh device id sst34hf324g bk0001h 7353h t2.0 1310
6 data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g ?2006 silicon storage technology, inc. s71310-00-000 6/06 figure 1: functional block diagram 1310 b1.0 superflash memory (bank 1) i/o buffers superflash memory (bank 2) 4 mbit sram a 20 - a 0 dq 15 - dq 0 control logic bef# lbs# ubs# we# oe# bes# address buffers address buffers wp# rst#
data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g 7 ?2006 silicon storage technology, inc. s71310-00-000 6/06 table 3: dual-bank memory organization (1 of 2) sst34hf324g block block size address range x8 address range x16 bank 1 ba63 8 kw / 16 kb 3fc000h?3fffffh 1fe000h?1fffffh 24 kw / 48 kb 3f0000h?3fbfffh 1f8000h?1fdfffh ba62 32 kw / 64 kb 3e0000h?3effffh 1f0000h?1f7fffh ba61 32 kw / 64 kb 3d0000h?3dffffh 1e8000h?1effffh ba60 32 kw / 64 kb 3c0000h?3cffffh 1e0000h?1e7fffh ba59 32 kw / 64 kb 3b0000h?3bffffh 1d8000h?1dffffh ba58 32 kw / 64 kb 3a0000h?3affffh 1d0000h?1d7fffh ba57 32 kw / 64 kb 390000h?39ffffh 1c8000h?1cffffh ba56 32 kw / 64 kb 380000h?38ffffh 1c0000h?1c7fffh ba55 32 kw / 64 kb 370000h?37ffffh 1b8000h?1bffffh ba54 32 kw / 64 kb 360000h?36ffffh 1b0000h?1b7fffh ba53 32 kw / 64 kb 350000h?35ffffh 1a8000h?1affffh ba52 32 kw / 64 kb 340000h?34ffffh 1a0000h?1a7fffh ba51 32 kw / 64 kb 330000h?33ffffh 198000h?19ffffh ba50 32 kw / 64 kb 320000h?32ffffh 190000h?197fffh ba49 32 kw / 64 kb 310000h?31ffffh 188000h?18ffffh ba48 32 kw / 64 kb 300000h?30ffffh 180000h?187fffh bank 2 ba47 32 kw / 64 kb 2f0000h?2fffffh 178000h?17ffffh ba46 32 kw / 64 kb 2e0000h?2effffh 170000h?177fffh ba45 32 kw / 64 kb 2d0000h?2dffffh 168000h?16ffffh ba44 32 kw / 64 kb 2c0000h?2cffffh 160000h?167fffh ba43 32 kw / 64 kb 2b0000h?2bffffh 158000h?15ffffh ba42 32 kw / 64 kb 2a0000h?2affffh 150000h?157fffh ba41 32 kw / 64 kb 290000h?29ffffh 148000h?14ffffh ba40 32 kw / 64 kb 280000h?28ffffh 140000h?147fffh ba39 32 kw / 64 kb 270000h?27ffffh 138000h?13ffffh ba38 32 kw / 64 kb 260000h?26ffffh 130000h?137fffh ba37 32 kw / 64 kb 250000h?25ffffh 128000h?12ffffh ba36 32 kw / 64 kb 240000h?24ffffh 120000h?127fffh ba35 32 kw / 64 kb 230000h?23ffffh 118000h?11ffffh ba34 32 kw / 64 kb 220000h?22ffffh 110000h?117fffh ba33 32 kw / 64 kb 210000h?21ffffh 108000h?10ffffh ba32 32 kw / 64 kb 200000h?20ffffh 100000h?107fffh ba31 32 kw / 64 kb 1f0000h?1fffffh 0f8000h?0fffffh ba30 32 kw / 64 kb 1e0000h?1effffh 0f0000h?0f7fffh ba29 32 kw / 64 kb 1d0000h?1dffffh 0e8000h?0effffh ba28 32 kw / 64 kb 1c0000h?1cffffh 0e0000h?0e7fffh ba27 32 kw / 64 kb 1b0000h?1bffffh 0d8000h?0dffffh ba26 32 kw / 64 kb 1a0000h?1affffh 0d0000h?0d7fffh ba25 32 kw / 64 kb 190000h?19ffffh 0c8000h?0cffffh ba24 32 kw / 64 kb 180000h?18ffffh 0c0000h?0c7fffh ba23 32 kw / 64 kb 170000h?17ffffh 0b8000h?0bffffh ba22 32 kw / 64 kb 160000h?16ffffh 0b0000h?0b7fffh
8 data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g ?2006 silicon storage technology, inc. s71310-00-000 6/06 figure 2: pin assignments for 48-ball lfbga (6mm x 8mm) bank 2 ba21 32 kw / 64 kb 150000h?15ffffh 0a8000h?0affffh ba20 32 kw / 64 kb 140000h?14ffffh 0a0000h?0a7fffh ba19 32 kw / 64 kb 130000h?13ffffh 098000h?09ffffh ba18 32 kw / 64 kb 120000h?12ffffh 090000h?097fffh ba17 32 kw / 64 kb 110000h?11ffffh 088000h?08ffffh ba16 32 kw / 64 kb 100000h?10ffffh 080000h?087fffh ba15 32 kw / 64 kb 0f0000h?0fffffh 078000h?07ffffh ba14 32 kw / 64 kb 0e0000h?0effffh 070000h?077fffh ba13 32 kw / 64 kb 0d0000h?0dffffh 068000h?06ffffh ba12 32 kw / 64 kb 0c0000h?0cffffh 060000h?067fffh ba11 32 kw / 64 kb 0b0000h?0bffffh 058000h?05ffffh ba10 32 kw / 64 kb 0a0000h?0affffh 050000h?057fffh ba9 32 kw / 64 kb 090000h?09ffffh 048000h?04ffffh ba8 32 kw / 64 kb 080000h?08ffffh 040000h?047fffh ba7 32 kw / 64 kb 070000h?07ffffh 038000h?03ffffh ba6 32 kw / 64 kb 060000h?06ffffh 030000h?037fffh ba5 32 kw / 64 kb 050000h?05ffffh 028000h?02ffffh ba4 32 kw / 64 kb 040000h?04ffffh 020000h?027fffh ba3 32 kw / 64 kb 030000h?03ffffh 018000h?01ffffh ba2 32 kw / 64 kb 020000h?02ffffh 010000h?017fffh ba1 32 kw / 64 kb 010000h?01ffffh 008000h?00ffffh ba0 32 kw / 64 kb 000000h?00ffffh 000000h?007fffh t3.0 1310 table 3: dual-bank memory organization (continued) (2 of 2) sst34hf324g block block size address range x8 address range x16 1310 48-lfbga l3k p1a.0 sst34hf324g top view (balls facing down) 6 5 4 3 2 1 a b c d e f g h a13 a9 we# bes# a7 a3 a12 a8 rst# wp# a17 a4 a14 a10 lbs# a18 a6 a2 a15 a11 a19 a20 a5 a1 a16 dq7 dq5 dq2 dq0 a0 ubs# dq14 dq12 dq10 dq8 bef# dq15 dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss
data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g 9 ?2006 silicon storage technology, inc. s71310-00-000 6/06 table 4: pin description symbol pin name functions a ms 1 to a 0 address inputs to provide flash address, a 20 -a 0 . to provide sram address, a 17 -a 0 dq 15 -dq 0 data inputs/outputs to output da ta during read cycles and receive input data during write cycles. data is internally latched during a flash erase/program cycle. the outputs are in tri-state wh en oe#, bes#, and bef# are high. bef# flash memory bank enable to activate the flash memory bank when bef# is low bes# sram memory bank enable to activate the sram memory bank when bes# is low oe# output enable to gate the data output buffers we# write enable to control the write operations ubs# upper byte control (sram) to enable dq 15 -dq 8 lbs# lower byte control (sram) to enable dq 7 -dq 0 wp# write protect to protect and unprotect the bottom 8 kword (4 sectors) from erase or program operation rst# reset to reset and return the device to read mode v ss ground v dd power supply 2.7-3.3v power supply t4.0 1310 1. a ms = most significant address
10 data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g ?2006 silicon storage technology, inc. s71310-00-000 6/06 table 5: operational modes selection for sram mode bef# 1 bes# 1,2 oe# 2 we# 2 lbs# 2 ubs# 2 dq 15-0 dq 15-8 full standby v ih v ih x x x x high-z high-z high-z xxxxx output disable v ih v il v ih v ih x x high-z high-z high-z v il xxv ih v ih v il v ih v ih v ih x x high-z high-z high-z x flash read v il v ih v il v ih xxd out d out dq 15-8 =high-z x flash write v il v ih v ih v il xxd in d in dq 15-8 =high-z x flash erase v il v ih v ih v il xx x x x x sram read v ih v il v il v ih v il v il d out d out d out v ih v il high-z d out d out v il v ih d out high-z high-z sram write v ih v il xv il v il v il d in d in d in v ih v il high-z d in d in v il v ih d in high-z high-z product identification 3 v il v ih v il v ih x x manufacturer?s id 4 device id 4 t5.0 1310 1. do not apply bef# = v il and bes# = v il at the same time 2. x can be v il or v ih, but no other value. 3. software mode only 4. with a 20 -a 18 = v il; sst manufacturer?s id = bfh, is read with a 0 =0, sst34hf324g device id = 7353h, is read with a 0 =1
data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g 11 ?2006 silicon storage technology, inc. s71310-00-000 6/06 table 6: software command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 program 555h aah 2aah 55h 555h a0h wa 3 data sector-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa x 4 50h block-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h ba x 4 30h chip-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h erase-suspend xxxxh b0h erase-resume xxxxh 30h software id entry 5 555h aah 2aah 55h bk x 6 555h 90h software id exit 555h aah 2aah 55h 555h f0h software id exit xxh f0h t6.0 1310 1. address format a 10- a 0 (hex), addresses a 20 -a 11 can be v il or v ih , but no other value, for the command sequence. 2. dq 15 -dq 8 can be v il or v ih , but no other value, for the command sequence 3. wa = program word address 4. sa x for sector-erase; uses a 20 -a 11 address lines ba x for block-erase; uses a 20 -a 15 address lines bkx for bank address; uses a 20 -a 15 address lines 5. the device does not remain in software product identification mode if powered down. 6. a 20 -a 18 = v il absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +125c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.3v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to v dd +1.0v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. operating range range ambient temp v dd commercial 0c to +70c 2.7-3.3v extended -20c to +85c 2.7-3.3v ac conditions of test input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 18 and 19
12 data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g ?2006 silicon storage technology, inc. s71310-00-000 6/06 table 7: dc operating characteristics (v dd = v ddf and v dds = 2.7-3.3v) symbol parameter limits test conditions min max units i dd 1 1. see figure 18 active v dd current address input = v ilt /v iht, at f=5 mhz, v dd =v dd max, all dqs open read oe#=v il , we#=v ih flash 15 ma bef#=v il , bes#=v ih sram 10 ma bef#=v ih , bes#=v il concurrent operation 45 ma bef#=v ih , bes#=v il write 2 2. i dd active while erase or program is in progress. we#=v il flash 40 ma bef#=v il , bes#=v ih , oe#=v ih sram 30 ma bef#=v ih , bes#=v il i sb standby v dd current 30 a v dd = v dd max, bef#=bes#=v ihc i rt reset v dd current 30 a rst#=gnd i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i liw input leakage current on wp# pin and rst# pin 10 a wp#=gnd to v dd , v dd =v dd max rst#=gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v dd =v dd max v ih input high voltage 0.7 v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol flash and sram output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh flash and sram output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t7.0 1310
data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g 13 ?2006 silicon storage technology, inc. s71310-00-000 6/06 table 8: recommended system power-up timings symbol parameter minimum units t pu-read 1 power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t8.0 1310 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. table 9: capacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 20 pf c in 1 input capacitance v in = 0v 16 pf t9.0 1310 table 10: flash reliability characteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t10.0 1310
14 data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g ?2006 silicon storage technology, inc. s71310-00-000 6/06 ac characteristics table 11: sram read cycle timing parameters symbol parameter min max units t rcs read cycle time 70 ns t aas address access time 70 ns t bes bank enable access time 70 ns t oes output enable access time 35 ns t byes ubs#, lbs# access time 70 ns t blzs 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. bes# to active output 0 ns t olzs 1 output enable to active output 0 ns t bylzs 1 ubs#, lbs# to active output 0 ns t bhzs 1 bes# to high-z output 25 ns t ohzs 1 output disable to high-z output 25 ns t byhzs 1 ubs#, lbs# to high-z output 35 ns t ohs output hold from address change 10 ns t11.0 1310 table 12: sram write cycle timing parameters symbol parameter min max units t wcs write cycle time 70 ns t bws bank enable to end-of-write 60 ns t aws address valid to end-of-write 60 ns t asts address set-up time 0 ns t wps write pulse width 60 ns t wrs write recovery time 0 ns t byws ubs#, lbs# to end-of-write 60 ns t odws output disable from we# low 30 ns t oews output enable from we# high 0 ns t dss data set-up time 30 ns t dhs data hold from write time 0 ns t12.0 1310
data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g 15 ?2006 silicon storage technology, inc. s71310-00-000 6/06 table 13: flash read cycle timing parameters v dd = 2.7-3.3v symbol parameter min max units t rc read cycle time 70 ns t ce chip enable access time 70 ns t aa address access time 70 ns t oe output enable access time 35 ns t clz 1 bef# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 bef# high to high-z output 16 ns t ohz 1 oe# high to high-z output 16 ns t oh 1 output hold from address change 0 ns t rp 1,2 rst# pulse width 500 ns t rhr 1,2 rst# high before read 50 ns t ry 1,2,3 rst# pin low to read 20 s t13.0 1310 1. this parameter is measured only for init ial qualification and after the design or pr ocess change that could affect this param eter. 2. l3k package only 3. this parameter applies to sector-erase, block-erase and pr ogram operations. this parameter does not apply to chip-erase. table 14: flash program/erase cycle timing parameters symbol parameter min max units t bp program time 12 s t as address setup time 0 ns t ah address hold time 40 ns t cs we# and bef# setup time 0 ns t ch we# and bef# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp bef# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. we# pulse width high 30 ns t cph 1 bef# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t es erase-suspend latency 10 s t br 1 bus# recovery time 1s t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 50 ms t14.1 1310
16 data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g ?2006 silicon storage technology, inc. s71310-00-000 6/06 figure 3: sram read cycle timing diagram figure 4: sram write cycle timing diagram (we# controlled) addresses a mss-0 dq 15-0 ubs#, lbs# oe# bes# t rcs t aas t bes t oes t blzs t olzs t byes t bylzs t byhzs data valid t ohzs t bhzs t ohs 1310 f02.0 note: a mss = most significant address a mss = a 17 for sst34hf324g t aws addresses a mss 3 -0 bes# we# ubs#, lbs# t wps t wrs t wcs t asts t bws t byws t odws t oews t dss t dhs 1310 f03.0 note 2 note 2 dq 15-8, dq 7-0 valid data in note: 1. if oe# is high during the write cycle, the outputs will remain at high impedance. 2. if bes# goes low coincident with or after we# goes low, the output will remain at high impedance. if bes# goes high coincident with or before we# goes high, the output will remain at high impedance. because d in signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. a mss = most significant sram address a mss = a 17 for sst34hf324g
data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g 17 ?2006 silicon storage technology, inc. s71310-00-000 6/06 figure 5: sram write cycle timing diagram (ubs#, lbs# controlled) figure 6: flash read cycle timing diagram addresses a mss 3 -0 we# bes# t bws t aws t wcs t wps t wrs t asts t byws dq 15-8, dq 7-0 valid data in t dss t dhs ubs#, lbs# 1310 f04.0 note 2 note 2 note: 1. if oe# is high during the write cycle, t he outputs will remain at high impedance. 2. because d in signals may be in the output state at this time, i nput signals of reverse polarity must not be applied. 3. a mss = most significant sram address a mss = a 17 for sst34hf324g 1310 f05.0 address a20 -0 dq 15-0 we# oe# bef# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz
18 data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g ?2006 silicon storage technology, inc. s71310-00-000 6/06 figure 7: flash we# controlled program cycle timing diagram figure 8: flash bef# controlled program cycle timing diagram 1310 f06.0 address a 20 -0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs ? bef# 555 2aa 555 addr xxaa xx55 xxa0 data word (addr/data) oe# we# t bp note: x can be v il or v ih , but no other value. valid valid 1310 f07.0 address a 20-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs ? we# 555 2aa 555 addr xxaa xx55 xxa0 data word (addr/data) oe# bef# t bp note: x can be v il or v ih , but no other value.
data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g 19 ?2006 silicon storage technology, inc. s71310-00-000 6/06 figure 9: flash data# polling timing diagram figure 10: flash toggle bit timing diagram 1310 f08.0 address a 20-0 dq 7 data data# data# data we# oe# bef# t oeh t oe t ce t oes 1310 f09.0 address a 20 -0 dq 6 we# oe# bef# t oe t oeh t ce two read cycles with same outputs valid data t br
20 data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g ?2006 silicon storage technology, inc. s71310-00-000 6/06 figure 11: flash we# controlled chip-erase timing diagram figure 12: flash we# controlled block-erase timing diagram valid 1310 f10.0 address a 20-0 dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx10 xx55 xxaa xx80 xxaa 555 oe# bef# six-byte code for chip-erase t sce t wp note: this device also supports bef# controlled chip-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are met. (see table 14.) x can be v il or v ih, but no other value. 1310 f11.0 address a 20-0 dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx30 xx55 xxaa xx80 xxaa ba x oe# bef# six-byte code for block-erase t wp valid t be note: this device also supports bef# controlled block-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are met. (see table 14.) ba x = block address x can be v il or v ih, but no other value.
data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g 21 ?2006 silicon storage technology, inc. s71310-00-000 6/06 figure 13: flash we# controlled sector-erase timing diagram figure 14: flash software id entry and read 1310 f12.0 address a 20-0 dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx50 xx55 xxaa xx80 xxaa sa x oe# bef# six-byte code for sector-erase t wp valid t se note: this device also supports bef# controlled sector-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are met. (see table 14.) sa x = sector address x can be v il or v ih, but no other value. 1310 f13.0 addresses t ida dq 15-0 we# 555 2aa 555 0000 0001 oe# bef# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 note: x can be v il or v ih, but no other value. device id - 7353h for sst34hf324g
22 data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g ?2006 silicon storage technology, inc. s71310-00-000 6/06 figure 15: flash software id exit 1310 f14.0 addresses dq 15-0 t ida t wp t wph we# 555 2aa 555 three-byte sequence for software id exit and reset oe# ce# xxaa xx55 xxf0 note: x can be v il or v ih , but no other value.
data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g 23 ?2006 silicon storage technology, inc. s71310-00-000 6/06 figure 16: rst# timing (when no inte rnal operation is in progress) figure 17: rst# timing (during sector- or block-erase operation) 1310 f15.0 ry/by# 0v rst# bef#/oe# t rp t rhr 1310 f16.0 ry/by# bef# oe# t rp t ry t br rst#
24 data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g ?2006 silicon storage technology, inc. s71310-00-000 6/06 figure 18: ac input/output reference waveforms figure 19: a test load example 1310 f17.0 reference points output input? v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1310 f18.0 to tester to dut c l
data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g 25 ?2006 silicon storage technology, inc. s71310-00-000 6/06 figure 20: program algorithm 1310 f19.0 start load data: xxaah address: 555h load data: xx55h address: 2aah load data: xxa0h address: 555h load address/data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih , but no other value.
26 data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g ?2006 silicon storage technology, inc. s71310-00-000 6/06 figure 21: wait options 1310 f20.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same byte/word data# polling program/erase completed program/erase completed read byte/word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g 27 ?2006 silicon storage technology, inc. s71310-00-000 6/06 figure 22: software product id command flowcharts 1310 f21.0 load data: xxaah address: 555h software product id entry command sequence load data: xx55h address: 2aah load data: xx90h address: 555 wait t ida read software id load data: xxaah address: 555h software id exit command sequence load data: xx55h address: 2aah load data: xxf0h address: 555h wait t ida return to normal operation note: x can be v il or v ih, but no other value.
28 data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g ?2006 silicon storage technology, inc. s71310-00-000 6/06 figure 23: erase command sequence 1310 f22.0 load data: xxaah address: 555h chip-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx10h address: 555h load data: xxaah address: 555h wait t sce chip erased to ffffh load data: xxaah address: 555h sector-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx30h address: sa x load data: xxaah address: 555h wait t se sector erased to ffffh load data: xxaah address: 555h block-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx50h address: ba x load data: xxaah address: 555h wait t be block erased to ffffh note: x can be v il or v ih, but no other value.
data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g 29 ?2006 silicon storage technology, inc. s71310-00-000 6/06 product ordering information valid combinations for sst34hf324g sst34hf324g-70-4c-l3ke SST34HF324G-70-4E-L3KE note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. package attribute e 1 = non-pb package modifier k = 48 balls package type l3 = lfbga (6mm x 8mm x 1.4mm, 0.45mm ball size) temperature range c = commercial = 0c to +70c e = extended = -20c to +85c minimum endurance 4 =10,000 cycles read access speed 70 = 70 ns version g = flash wp# and rst# + sram sram density 4 = 4 mbit flash density 32 = 32mbit voltage h = 2.7-3.3v product series 34 = dual-bank flash + sram combomemory 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?. device speed suffix1 suffix2 sst34 h f324g - xxx -x x -xx x x
30 data sheet 32 mbit dual-bank flash + 4 mbit sram combomemory sst34hf324g ?2006 silicon storage technology, inc. s71310-00-000 6/06 packaging diagrams 48-ball low-profile, fine-pitch ba ll grid array (lfbga) 6mm x 8mm sst package code: l3k h g f e d c b a a b c d e f g h bottom view top view side view 6 5 4 3 2 1 6 5 4 3 2 1 seating plane 0.35 0.05 1.30 0.10 0.12 0.80 4.00 0.80 5.60 48-lfbga-l3k-6x8-450mic-5 note: 1. except for total height dimension, complies with jedec publication 95, mo-210, variant 'ab-1', although some dimensions may be more stringent. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 1mm 0.45 0.05 (48x) a1 corner 6.00 0.20 a1 corner 8.00 0.20 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com table 15: revision history number description date 00 ? initial release jun 2006

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